1. Field of Invention
The present invention relates to the design of ICs (integrated circuits) generally and more particularly to the design of analog and RF (radio frequency) ICs.
2. Description of Related Art
Stringent performance requirements combined with internal sensitivities have created challenges for conventional IC design and especially for analog and RF designs. For example, RF designs are relatively sensitive to interconnect parasitics, and as a result the capacitance, inductance and resistance of wires between devices can have a significant impact on the electrical performance of an RF circuit. Similar challenges are found in the context of analog IC design.
A regular circuit schematic consists of devices (e.g., resistors, capacitors, transistors). When such a schematic is simulated, the impact of interconnect parasitics is typically not taken into account. In a typical IC design flow, this impact is only known at the very end of the design cycle when the layout is complete and the interconnect parasitics are extracted via layout parasitic extraction (LPE). The extracted netlist is then simulated. For RF designs, oftentimes, the design fails to meet the targeted specifications when the deleterious effects of interconnect are accounted for. A typical RF IC design process might require at least six passes through schematic sizing, layout and LPE. This reduces productivity and lengthens time to market.
FIG. 1 shows a conventional manual method 100 for IC design. First a schematic sizing 102 is carried out. Then simulations 104 are carried out in order to test 106 whether the preliminary performance specifications have been met. If not, then the schematic sizing 102 is repeated followed by simulation 104 until the preliminary performance test 106 is passed. In practice this stage may require twenty or more iterations.
Next a layout is generated 108 followed by estimation of layout parasitics 110 and simulation 112 in order to test 114 whether the final performance specifications are satisfied. If not, the process is restarted with the generation 108 of another layout (or the schematic sizing 102) until the final performance test 114 is passed. In practice this stage may require six or more iterations. After the final test 114 is passed, a tape-out 116 can be done.
Variations in these process steps are also known, for example, for automating at least some of the process steps. A conventional automated method 118 for IC design combines schematic sizing 102, simulation 104 and a preliminary performance test 106 into an automated sizing process 120, which again might require twenty or more internal iterations for convergence. An automated layout step 122 is then followed by layout parasitic extraction 124, simulation 126 and a final performance test 128 before a tape-out 130. Similarly as in the other method 100, six or more iterations may be required to meet the final performance test 128.
As discussed above, this design process can be cumbersome in important contexts with stringent performance requirements and internal sensitivities (e.g., for analog ICs and RF ICs). There have been attempts at constraining the layout so that the parasitics introduced do not exceed pre-computed limits that are set to ensure that the circuit continues to meet performance specifications after layout. (U. Choudhury, A. Sangiovanni-Vincentelli, “Automatic Generation of Parasitic Constraints for Performance-Driven Physical Design of Analog Circuits”, IEEE Trans. on Comp. Aided Design, vol. CAD-12, n. 2, pp. 208-224, February 1993.) In general, however, these solutions have remained academic exercises and have failed to materialize as practical solutions because the constraints thus generated are not realizable in layout.
Thus, there is a need for IC design methods that consider the impact of parasitics at the time of sizing by simultaneously creating a layout as part of an integrated process.